Present complementary metal oxide semiconductor (CMOS) circuits are frequently used for a variety of computer applications. Among the many uses, CMOS circuits are used in memory devices. Among memory devices, two general types are do random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs). Unlike typical DRAMs which use internal clock signals generated from he standard row address strobe (RAS.sub.--) and column address strobe (CAS.sub.--) signals issue by the microprocessor, SDRAMs use timing signals generated from the external system clock (which is the same clock the microprocessor uses). Hence, SDRAMs may operate at a much higher speed than DRAMs. U.S. Pat No. 5,386,385, issued Jan. 31, 1995, entitled "Method and Apparatus for Preventing Invalid Operating Modes and an Application To Synchronous Memory Devices", assigned to Texas Instruments Incorporated, discloses a SDRAM.
The SDRAM has an on-chip column address counter to facilitate access to the addressed memory cells. In operation, the first column address is provided to the SDRAM, and an internal counter generates subsequent column address locations based on a predetermined counting (Serial or Interleave) method and burst length.
In a column address counter, N counting circuits are required for a 2.sup.N burst length. For example, eight counting circuits are required for a 256 bit burst. In a Serial counting method, when the counter reaches it's maximum count, all bits must roll over to all zeros. To accomplish the maximum to minimum transition, a signal (the carry bit) may have to ripple through an counting stages. Under high speed operation, this ripple delay may cause a bottleneck.
Traditional methods for improving the delay caused by the carry bit ripple has been to use look-ahead circuitry to anticipate when a carry is needed. Unfortunately, a pathological case exists when the first address loaded on the SDRAM is the maximum counting value. The look-ahead circuitry itself must ripple through a signal since it has no prior knowledge of the counter's status. As the system clock speed increases and/or the depth of the burst length is large, the ability to use column address counters is limited. What is required is a method to substantially reduce the number of stages a ripple signal must traverse.
It is accordingly an object of the invention to improve access speed to addressed memory cells. Other objects and advantages of the invention will be apparent to those possessing ordinary skill in the art having the benefit of the specification and drawings herein.